1) Field of the Invention
The present invention relates to a layout designing apparatus, a layout designing method, and a layout designing program for designing a large-scale-integrated (LSI) chip, suppressing a delay time caused by a crosstalk.
2) Description of the Related Art
Conventionally, increase of work efficiency in an LSI design by shortening a design period is demanded. Particularly, for an LSI that requires large-scale, high performance, high-speed, and low-power consumption, it is important to increase the work efficiency in designing work to maintain a high quality.
Therefore, conventionally in the LSI design, an amount of crosstalk that occurs between nets wired adjacent to each other is calculated and analyzed after routing a wiring. A buffer is applied to resolve the crosstalk error to the nets in which the crosstalk error occurs (conventional technology 1).
The crosstalk error is also corrected by rearranging a part of wirings that are arranged in parallel instead of applying the buffer (conventional technology 2).
Furthermore, the crosstalk error is prevented by arranging the wiring in such a manner that the wiring has a wire length that is less likely to be influenced by the crosstalk. In other words, when the wiring is arranged, a wire length that is likely to cause the crosstalk error is avoided in advance in a process performed manually, and an extra number of relay buffers are arranged in the wiring during logic designing (conventional technology 3).
Data of cell arrangement is obtained after automatically arranging the wiring. Then, a length of a parallel wiring that is formed by connecting temporary wirings in a manhattan length path between cell terminals in an identical node is determined before automatically arranging a wiring between the cells. The crosstalk error in a parallel wiring that is longer in length than a predetermined length is detected. The crosstalk is corrected by rearranging the cells that are arranged closely at intervals within a predetermined value, and that are connected to a temporary wiring in which the crosstalk is detected, or by applying the buffer (conventional technology 4). Such a technology is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-281212.
However, in the above conventional technology 1, the buffer is applied to reduce the crosstalk error in a certain area in which the crosstalk error is detected after automatically routing the wiring. Therefore, if there is no space for arranging the buffer in the area, it is necessary to route the wring from a beginning. Thus, turn around time (TAT) increases.
Moreover, in the above conventional technology 2, the crosstalk error is detected after automatically routing the wiring, and the wiring in an area in which the crosstalk error occurs is rerouted to reduce the crosstalk error. If the wiring is congested in the area, it is necessary to reroute the wiring from the beginning because a short circuit may be caused in the area with another wiring that has been routed in the area. Thus, the TAT increases.
Furthermore, in the conventional technology 3, an extra process is required manually during designing a wiring layout to avoid the crosstalk error. Therefore, a great number of work procedures are required. In addition, it is necessary to consider a floor plan even from a stage of the logic designing. Thus, designing becomes complicated due to such limits in designing, and the number of required procedures increases.
Moreover, in the conventional technology 4, the crosstalk error is detected after automatically routing the wiring to correct the crosstalk error. If the wiring is congested in an area in which the crosstalk error is detected, or if there is no space left for the buffer in the area, it is impossible to apply the buffer or rearrange the cells. Therefore, it is necessary to rearrange the cells from the beginning. As a result, the TAT increases.
In addition, even if the crosstalk error is corrected in an area by applying the buffer or by rearranging the cells, this causes delay in a net that is interactively connected to the area. Moreover, mountability of the layout decreases.